TARGET PROCESSORS

As of the date of this document, NoICE for Windows supports the following processors:

Motorola/Freescale 68HC12 Family

Motorola/Freescale 68HC08 Family

Motorola/Freescale 68HC11 Family

Motorola 6809

Texas Instruments MSP430

Intel 8051

Zilog Z80, Z85C1X, Z180 Family

Rockwell / Western Design Center 6502, 65C02 Family

Intel 8096/80196 Family

Intel 8080/8085

Other Processors


Intel 8051

NoICE for the 8051 uses the NoICE Serial Protocol communicating with a target monitor.

This processor has several distinct address spaces: on-chip RAM, SFR, on-chip program, off-chip program, and off-chip data. As the 8051 does not have an instruction to write to code memory, the target monitor uses the MOVX instructions to read and write off-chip code or data memory. In order for MOVX to access program memory, PSEN and RD must be combined via external hardware, or appropriate control of the appropriate chip selects must be provided. This may be done to yield a single 64K address space including both program and data memory, or distinct memory banks may be maintained.

For simplicity, the basic target monitors assume that program and data memory are combined. This is a popular model for Single Board Computers which have hex monitors. Consult your documentation to see how your SBC is configured. The basic monitors map a single 16 bit address as follows: Addresses below 0100 hex are regarded as specifying on-chip RAM. Note that the 8051 distinguishes between direct and indirect addressing for RAM locations 80 to 0FF hex: direct addressing accesses Special Function Registers (SFR's), while indirect addressing accesses RAM. The basic target monitors will access on-chip RAM if memory addresses in the range 80 to 0FF hex are specified. In order to access SFR's, the IN and OUT commands must be used.

Addresses 100 hex and above access external program/data memory. The low 100 hex bytes of program/data memory are not accessible via the serial link. This is not regarded as a problem, as this region will typically be where the target monitor resides.

If support for external data memory as distinct from program memory is desired, it may be implemented by using memory pages. For example, the paged region could be specified as 0000 to 0ffff hex; with page 0 being register memory, page 1 program memory, and page 2 external data memory. Suitable modifications of the target monitor (and target hardware) would be required, but no changes are required to NoICE51. For mnemonic convenience, the paged target monitors provided with NoICE assign page 0 to register memory, page B to bit memory, page C to code memory, and page D to external data memory. The page equates are found near the top of the source file, so that you may change them if you so desire. (If you change them, and you use OMF51NOI.EXE or MAPNOI.EXE, you may use command line parameters to change the page information output by these utilities as well.)

Unlike any of the other processors supported by NoICE, the 8051 is not clearly MSB-first or LSB-first. LJMP and LCALL fetch addresses most significant byte first. However, as the 8051 has no instruction which loads or stores 16 bit data, the byte order for data is up to the programmer. Some C compilers follow the "native" order for multi-byte data. However, this can be expensive in terms of program space, since the 8051 cannot decrement its DPTR register. Thus, other C compilers store multi-byte data least significant byte first. In order to WATCH and EDIT such data in the correct byte order, NoICE must be told to change the order. This may be done using the MSBFIRST command.

Registers supported are R0 through R7, A, B, PSW, DPTR, SP, PC, and PG if paged memory is used. In addition, register "RB" denotes the register bank bits of the PSW, and register "IE" the interrupt enable SFR. The master interrupt control bit of the actual IE SFR is cleared upon entry to the monitor, and restored from the IE register when a user program is executed. In order to preserve proper monitor operation, the actual IE SFR should not be changed using NoICE memory or input/output commands. All such changes should be made to the IE register.

Except for RESET, the standard monitor routes interrupts through a region of RAM which duplicates low memory. This region is initialized with jumps which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor.

Unique processor states are reported in the title bar for
0RESET
1BREAKPOINT
2IE0
3TF0
4IE1
5TF1
6RI & TI
7TF2 & EXF2
8Int 0033
9Int 003B
10IADC: A/D Converter
11IEX2: External Int 2
12IEX3: External Int 3
13IEX4: External Int 4
14IEX5: External Int 5
15IEX6: External Int 6
16Int 0073
17Wake-up from power-down mode
18RI1 & TI1: Serial 1
19CAN Controller
20SSC Interface
21CTF: Compare Timer Overflow
22IEX7: External Int 7
23IEX8: External Int 8

Other processor state values will be shown numerically. Note that not all of these interrupts exist on some members of the processor family. You can change the default strings for any interrupt by means of the STATETEXT command.

The 8051 unfortunately has no single-byte op-code suitable for use as a breakpoint instruction. Thus, NoICE uses a three byte "LCALL" (hex 12) instruction. This has the effect that breakpoints cannot be placed more closely than three bytes apart, as the inserted breakpoint instructions would overlap. NoICE will prevent the insertion of a breakpoint which would overlap another.

Since single-step is implemented using breakpoints, there may be instructions, such as short forward or backward branches, which cannot be stepped due to overlapped breakpoints.

Several monitors are provided. Most are about 1K bytes in length, including I/O initialization. The monitors uses 256 bytes or less of RAM, but requires no on-chip RAM other than the current register bank, the original contents of which are saved while in the monitor. The monitors are:

Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.

Additional information is available about customizing target monitors


Motorola/Freescale 68HC11 Family

NoICE for the 68HC11 uses the NoICE Serial Protocol communicating with a target monitor.

Registers supported are A, B, D, X, Y, SP, PC, CC, and PG if paged memory is used.

In the standard monitor, interrupts for RESET, CLOCK FAIL, COP, ILLEGAL OP-CODE, SWI and XIRQ enter the monitor and report a processor state which names the interrupt. All other interrupts are routed through RAM vectors. These RAM vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.

Unique processor states are reported in the title bar for
0RESET
1BREAKPOINT (SWI)
2XIRQ
3Clock Monitor
4COP Fail
5Illegal Op-code
6IRQ
7Real Time Clock
8Timer Capture 1
9Timer Capture 2
10Timer Capture 3
11Timer Compare 1
12Timer Compare 2
13Timer Compare 3
14Timer Compare 4
15Timer Compare 5
16Timer Overflow
17Pulse Accumulator Overflow
18Pulse Accumulator Edge
19SPI
20SCI

Other processor state values will be shown numerically.

While the single byte instruction SWI is preferred for use as a breakpoint instruction, JSR may be used with appropriate modification of the target monitor.

The basic monitor, MONHC11.ASM, is less than 1024 bytes in length, and uses about 256 bytes of RAM. The monitor may be assembled with the AS11 assembler available from Motorola/Freescale's Freeware BBS, or with the Dunfield assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.

The monitor BOTBD-E2.ASM is a modification of MONHC11 to support Marvin Green's Bot Board 2. Consult the monitor source code for further details.

Additional information is available about customizing target monitors


Motorola 6809

NoICE for the 6809 uses the NoICE Serial Protocol communicating with a target monitor.

Registers supported are A, B, D, X, Y, U, SP, PC, CC, and PG if paged memory is used.

In the standard monitor, interrupts for RESET and SWI enter the monitor and report a processor state which names the interrupt. All other interrupts are routed through RAM vectors. These RAM vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.

Unique processor states are reported in the title bar for
0RESET
1BREAKPOINT (SWI)
2NMI
3IRQ
4FIRQ
5SWI2
6SWI3

Other processor state values will be shown numerically.

While the single byte instruction SWI is preferred for use as a breakpoint instruction, SWI2, SWI3 or JSR may be used with appropriate modification of the target monitor. However, these multi-byte instructions will restrict where you can place breakpoints, so SWI is preferred.

The basic monitor, MON6809.ASM, is less than 1024 bytes in length, and uses about 256 bytes of RAM. The monitor may be assembled with the AS09 assembler available from Motorola/Freescale's Freeware BBS, or with the Dunfield assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.

Additional information is available about customizing target monitors


Zilog Z80, Z85C1X, Z180 Family

NoICE for the Z80/Z180 uses the NoICE Serial Protocol communicating with a target monitor.

In addition to the basic Z80 instruction set, the enhanced instructions for the Z85C1X and Z180 family are supported. Because of this, the disassembler may show instructions which are not compatible with a given target. For example, the IN0 instruction of the Z180 does not exist on the Z80 or Z85C1X. While the instruction will be disassembled, operation of single-step is not guaranteed for instructions not supported by a given target.

Registers supported are A, FL, AF, B, C, D, E, H, L, BC, DE, HL, IX, IY, SP, PC, I, IFF (interrupt enable flip flop), A', FL', AF', B', C', D', E', H', L', BC', DE', HL', and PG if paged memory is used.

Except for RESET and the RST instruction used for breakpoint, the standard monitor routes NMI and RSTnn interrupts through a region of RAM which duplicates low memory. This region is initialized with jumps which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor. If interrupt mode two (vectored) is used, interrupts will be independent of the monitor.

Unique processor states are reported in the title bar for
0RESET (RST 0)
1BREAKPOINT (RST nn)
2NMI
3RST 8
4RST 10
5RST 18
6RST 20
7RST 28
8RST 30
9RST 38
10TRAP (Z180 only)

Other processor state values will be shown numerically.

While the single byte instruction RST nn is preferred for use as a breakpoint instruction, a three byte CALL may be used with appropriate modification of the target monitor.

The monitor is less than 1024 bytes in length, including I/O initialization, and uses 256 bytes or less of RAM. The monitor MONZ80.S may be assembled with the Zilog ASM80 assembler formerly shipped with Zilog evaluation boards. The monitor MONZ80.ASM may be assembled with the PseudoSam Z80 assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.

Additional information is available about customizing target monitors


Rockwell / Western Design Center 6502, 65C02 Family

NoICE for the 65(C)02 uses the NoICE Serial Protocol communicating with a target monitor.

Registers supported are A, X, Y, SP, PC, CC, and PG if paged memory is used.

Except for RESET and BRK, interrupts in the standard monitor are routed through RAM vectors. These vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.

Unique processor states are reported in the title bar for
0RESET
1BREAKPOINT (BRK)
2NMI
3IRQ

Other processor state values will be shown numerically.

The monitor MON6502.ASM is less than 1024 bytes in length. The monitor uses 256 bytes or less of RAM, but requires no page 0 RAM. It contains only instructions from the basic 6502 set, and may be used on either 6502 or 65(C)02 variants. The monitor has been assembled with the Avocet AVMAC (tm) assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.

Additional information is available about customizing target monitors


Intel 8096/80196

NoICE for the 8096/80196 uses the NoICE Serial Protocol communicating with a target monitor.

NoICE96 supports both the 8096 and the 80196 instruction sets. The monitor contains no 80196-specific instructions, and only a few 80196-specific Special Function Register references. It should be easy to modify it for use on an 8096. However, no testing has been performed on an 8096.

The 80196 contains 256 bytes of directly addressable "Register File". This contains both Special Function Registers and general purpose RAM. Of these, the NoICE register window displays PC, SP, PSW, and PG if paged memory is used. Other locations in the Register File may be added to the register window using the DEFREG command, or placed in the watch window using the WATCH command.

The standard monitor supports horizontal windowing, but does not support vertical windowing. Support for vertical windowing may be added to the monitor by the user, if desired. However, since direct and indirect addressing will access different physical locations when vertical windowing is in use, the user must decide which form of address is to be used when the target "read memory" and "write memory" commands are used. In addition, use of direct addressing would require the use of self-modifying code.

Except for RESET, the standard monitor routes interrupts through a region of RAM which duplicates the layout of memory at address 2000h. This region is initialized with vectors to default handlers which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor.

Unique processor states are reported in the title bar for
0RESET
1BREAKPOINT
2Timer Overflow
3A/D Complete
4HSI Data Available
5High Speed Output
6HSI.O
7Software Timers
8Serial Port
9EXTINT
10Trap (if not used for breakpoint)
11Unimplemented Op-code
12TI
13RI
144th entry in HSI FIFO
15Timer2 Capture
16Timer2 Overflow
17EXTINT1
18HSI FIFO Full
19NMI

Other processor state values will be shown numerically. Note that not all of these interrupts exist on all members of the processor family.

The TRAP op-code (hex 0F7) is used as a breakpoint instruction.

The monitor is less than 1200 bytes in length, including I/O initialization. The monitor uses 256 bytes or less of RAM, but requires no on-chip RAM other than scratch registers, the original contents of which are saved while in the monitor. The monitor has been assembled with the PseudoSam ASM96 assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.

Thanks to Gene Pfister for the use of his 80196 target board, and for pointing out a number of errors in the original version of the 80196 monitor.


Intel 8080/8085

NoICE for the 8080/8085 uses the NoICE Serial Protocol communicating with a target monitor.

NoICE supports the 8085 instruction set including RIM and SIM. In addition, NoICE supports the well known "undocumented" 8085 instructions. Use of these instructions is at the users discretion.

Registers supported are A, FL, B, C, D, E, H, L, BC, DE, HL, SP, PC, IM (interrupt mask as read by RIM), and PG if paged memory is used. Note that only the lower four bits of IM may be written by NoICE.

Except for RESET and the RST instruction used for breakpoint, the standard monitor routes TRAP and RSTnn interrupts through a region of RAM which duplicates low memory. This region is initialized with jumps which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor. If interrupt mode two (vectored) is used, interrupts will be independent of the monitor.

Unique processor states are reported in the title bar for
0RESET (RST 0)
1BREAKPOINT (RST nn)
2RST 1
3RST 2
4RST 3
5RST 4
6RST 5
7RST 6
8RST 7
9RST 5.5
10RST 6.5
11RST 7.5
12TRAP
13RSTV

Other processor state values will be shown numerically.

While the single byte instruction RST nn is preferred for use as a breakpoint instruction, a three byte CALL may be used with appropriate modification of the target monitor.

The monitor is less than 1024 bytes in length, including I/O initialization, and uses 256 bytes or less of RAM. The monitor MON8085.ASM may be assembled with the Dunfield 8085 assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.

Additional information is available about customizing target monitors


Other Processors

Additional processors may be supported in the future, as time and interest allow. Some likely candidates are listed below. If you are interested in one of these, or wish to suggest another target, please contact us.

The DOS version of NoICE also supported the 6809, 6801/6301, 6805, MELPS740, TMS370, and H8/300. A version of NoICE for Windows for any of these processors could be done if there were sufficient interest. Please contact us to lobby for your favorite.

I would like to support the Microchip PIC and the Atmel AVR, but the architecture of both pretty much precludes the use of a monitor-based debugger. For the PIC in particular: code memory is wider than 8 bits, most members of the family have only a two level stack, and there is no way to push or pull data from the stack except for call and return. If you can think of a way around these problems, please contact us.


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